1. Field of the Invention
The present invention relates to a semiconductor device suitable for a SRAM and a manufacturing method of the same.
2. Description of the Related Art
Recently, miniaturization of a transistor is pursued for the purpose of high-density design and high performance of a semiconductor device. However, in a SRAM (Static Random Access Memory), the threshold voltage is reduced due to an inverse narrow channel effect when the channel width of the transistor which constitutes each memory cell (SRAM cell) is narrowed. As a result, the operation margin of the SRAM cell becomes small.
Patent document 1 (Japanese Patent Application Laid-open No. 2000-58675) discloses a method in which in order to enhance the threshold voltage of the transistor constituting an SPAM cell, a step of introducing an impurity into only the transistor is added besides the introduction of the impurity which is performed in parallel with formation of a logic circuit and an input and output circuit (I/O circuit).
Further, as described in Non-patent document 1 “The Impact of Technology Scaling on Soft Error Rate Performance and Limits Efficacy of Error Correction”, IEDM 2002, as the high-density design of a transistor advances, the soft error rate of the SRAM cell increases, and therefore higher soft error resistance is required.
A related art is described in Patent document 2 (Japanese Patent Application Laid-open No. Hei 11-74378).